“One Student One Chip” v24.07 Course Homepage
- Live teaching sessions will start in September 2025. Stay tuned.
- If you find errors in the lab handouts or materials, or have questions or suggestions about the experiments, please contact Yu Zihao via email (yuzihao#ict.ac.cn).
Learning Resources
- The
Timecolumn indicates estimated completion time in hours.- Content marked with an estimated completion time of
2typically does not include programming assignments, but consists of 2 hours of video lectures designed to supplement related knowledge. - Given varying student proficiency levels, these estimates are based on “intermediate-level” learners. This “intermediate level” does not mean “scoring above 80% in programming courses,” but rather “having a positive learning attitude, having written a single program exceeding 500 lines of code, and understanding debugging.”
- If you are a complete beginner, expect to spend 2–3 times this amount of time to complete the study. Don't be discouraged—as the saying goes, “Some learn earlier, some later.” The reason other students progress faster is largely because they've already invested effort to overcome the beginner stage.
- Content marked with an estimated completion time of
- Click icons to jump to corresponding resources
- Full lecture notes accessible via the top-right navigation bar
- Course materials created with reveal.js, exportable to PDF—see this guide
- S-stage lecture content remains under development 🕊
C = C language ( programs / emulators / system software ) | R = RISC-V instruction set | P = Processor design | T = Tools
| Stage | Number | Task | Time | Course Handout | Slide | Video | C | R | P | T |
|---|---|---|---|---|---|---|---|---|---|---|
| F Stage | How to Ask Smart Questions | 2 | 📚 | 📰 | 🎬 | |||||
| Installing and Using Logisim | 2 | 📚 | - | - | ||||||
| The basic of digital and logic circuits | 20 | 📚 | 📰 | 🎬 | ||||||
| State Machine Model of Computer Systems | 5 | 📚 | 📰 | 🎬 | ||||||
| Simple Processor Supporting Sequence Summation | 5 | 📚 | - | - | ||||||
| A Fully Functional Mini RISC-V Processor | 5 | 📚 | - | - | ||||||
| E Stage | C language programming | 20 | 📚 | 📰 | 🎬 | |||||
| Hardware Description Language | 20 | 📚 | 📰 | 🎬 | ||||||
| Linux System Installation and Basic Usage | 10 | 📚 | 📰 | 🎬 | ||||||
| From C Code to Binary Program | 10 | 📚 | 📰 | 🎬 | ||||||
| From RTL Code to Tapeout-Ready Layout | 20 | 📚 | - | - | ||||||
| Complete PA1 | 20 | 📚 | 📰 | 🎬 | ||||||
| Submission of pre-study defense application | ||||||||||
| D Stage | NEMU with RV32IM Support | 10 | 📚 | 📰 | 🎬 | |||||
| Machine-level representation of programs I | 2 | 📚 | 📰 | 🎬 | ||||||
| Machine-level representation of programs II | 2 | 📚 | 📰 | 🎬 | ||||||
| AM Runtime environment | 5 | 📚 | 📰 | 🎬 | ||||||
| Implementing a mini RISC-V Processor using RTL | 5 | 📚 | - | - | ||||||
| Devices and Input/Output | 10 | 📚 | 📰 | 🎬 | ||||||
| C Stage | Tools and Infrastructure | 5 | 📚 | 📰 | 🎬 | |||||
| RV32E Single Cycle NPC | 5 | 📚 | 📰 | 🎬 | ||||||
| Debugging Techniques | 2 | 📚 | 📰 | 🎬 | ||||||
| ELF Files and Linking | 2 | 📚 | 📰 | 🎬 | ||||||
| Exception Handling and RT-Thread | 15 | 📚 | 📰 | 🎬 | ||||||
| C Stage Completion Preparation and Assessment | ||||||||||
| B Stage | Bus | 10 | 📚 | 📰 | 🎬 | |||||
| SoC Computer System I | 15 | 📚 | 📰 | 🎬 | ||||||
| SoC Computer System II | 15 | 📚 | 📰 | 🎬 | ||||||
| Time Analysis and Optimization | 5 | 📚 | - | - | ||||||
| Performance Optimization and Simple Cache | 20 | 📚 | 📰 | 🎬 | ||||||
| Pipelined Processor | 20 | 📚 | 📰 | 🎬 | ||||||
| B Stage Tapeout Preparation and Assessment 📚 | ||||||||||
| A Stage | Multiplication and Division Module | 0 | ||||||||
| System Calls and Applications | 0 | |||||||||
| Virtual Memory Management | 0 | |||||||||
| Privilege Level and xv6 | 0 | |||||||||
| Booting Linux and Debian | 0 | |||||||||
| Advanced Cache | 0 | |||||||||
| Advanced Branch Prediction | 0 | |||||||||
| A Stage Tapeout Preparation and Assessment | ||||||||||
| S Stage | Under Construction ... | 0 | ||||||||
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Past Courses Homepage
Accessible via the “Courses Home" link in the top navigation bar.
Other Resources
- The RISC-V Reader: An Open Architecture Atlas By David Patterson and Andrew Wathelet
- Computer Systems: Based on the RISC-V + Linux Platform Edited by Yuan Chunfeng, Yu Zihao, and Chen Lu
- Digital Design and Computer Architecture - Spring 2023, Onur Mutlu@ETH Zurich
- Questioning template
Record of events
- 2024/07/14 - “One Student One Chip” 2024 Summer Workshop
- 2023/08/25 - Open Source Chip Technology Ecology Forum (formerly "One Student One Chip" Technology Forum)
- 2023/07/02 - 6th "One Student One Chip" Kick-Off Meeting
- 2022/11/20 - Chip Open Source and Agile Design from a Software Engineering Perspective(Yungang Bao)
- 2022/08/28 - The First "One Student One Chip" Technical Forum and the Fifth Launching Meeting
- 2022/03/12 - Hardware-software collaboration capabilities in chip design(Yue Jin, Bohan Hu, Zeyu Gao)