“One Student One Chip” v26.07 Course Homepage
- Class Time: Wait to be determined
- If you find errors in the lab handouts or materials, or have questions or suggestions about the experiments, please contact Yu Zihao via email (yuzihao#ict.ac.cn).
- Given that an increasing number of students are submitting incorrect AI-generated answers as modification suggestions, if no email response is received within one week, the suggestion will be considered not adopted by default.
Learning Resources
- The
Timecolumn indicates estimated completion time in hours.- Content marked with an estimated completion time of
2typically does not include programming assignments, but consists of 2 hours of video lectures designed to supplement related knowledge. - Given varying student proficiency levels, these estimates are based on “intermediate-level” learners. This “intermediate level” does not mean “scoring above 80% in programming courses,” but rather “having a positive learning attitude, having written a single program exceeding 500 lines of code, and understanding debugging.”
- If you are a complete beginner, expect to spend 2–3 times this amount of time to complete the study. Don't be discouraged—as the saying goes, “Some learn earlier, some later.” The reason other students progress faster is largely because they've already invested effort to overcome the beginner stage.
- Content marked with an estimated completion time of
- Click icons to jump to corresponding resources
- Full lecture notes accessible via the top-right navigation bar
- Course materials created with reveal.js, exportable to PDF—see this guide
- The S-stage lecture notes are still coming soon™. 🕊
C = C language ( programs / emulators / system software ) | R = RISC-V instruction set | P = Processor design | T = Tools
| Stage | Number | Task | Time | Course Handout | Slide | Video | C | R | P | T |
|---|---|---|---|---|---|---|---|---|---|---|
| F stage | F1 | How to Ask Smart Questions | 2 | 📚 | 📰 | 🎬 | ||||
| F2 | Installing and Using Logisim | 2 | 📚 | - | - | |||||
| F3 | Fundamentals of Digital Logic Circuits | 20 | 📚 | 📰Pt.1 📰Pt.2 | 🎬Pt.1 🎬Pt.2 | |||||
| F4 | State Machine Model of Computer Systems | 5 | 📚 | 📰 | 🎬 | |||||
| F5 | Simple Processor Supporting Sequence Summation | 5 | 📚 | 📰 | 🎬 | |||||
| F6 | Simple Basic Input/Output | 5 | 📚 | - | - | |||||
| F Stage Tapeout Preparation | ||||||||||
| E Stage | E1 | Hardware Description Language | 20 | 📚 | - | - | ||||
| E2 | C language programming | 20 | 📚 | - | - | |||||
| E3 | Linux System Installation and Basic Usage | 10 | 📚 | 📰 | 🎬 | |||||
| E4 | Processor Simulation and Verification | 5 | 📚 | - | - | |||||
| E5 | A Fully Functional mini RISC-V Processor | 5 | 📚 | - | - | |||||
| E6 | Simple Runtime Environment | 5 | 📚 | - | - | |||||
| E7 | Simple Bus and SoC | 5 | 📚 | - | - | |||||
| E8 | Synthesis and Physical Design | 5 | 📚 | - | - | |||||
| Submission of pre-study defense application | ||||||||||
| D Stage | D1 | From C to binary | 10 | 📚 | 📰 | 🎬 | ||||
| Execution of a C program | 📰 | 🎬 | ||||||||
| D2 | Simple Debugging Tool, SDB | 20 | 📚 | 📰 | 🎬 | |||||
| D3 | RISC-V Instruction Set Architecture | 5 | 📚 | 📰 | 🎬 | |||||
| D4 | The machine-level representation of a program | 4 | 📚 | 📰Pt.1 📰Pt.2 | 🎬Pt.1 🎬Pt.2 | |||||
| D5 | Abstract Machine Runtime Environment | 5 | 📚 | 📰 | 🎬 | |||||
| D6 | From RTL code to GDS | 20 | 📚 | 📰 | 🎬 | |||||
| Logic Synthesis | 📰 | 🎬 | ||||||||
| Verilog RTL Synthesis Semantics | 📰 | 🎬 | ||||||||
| Standard Cell Library | 📰 | 🎬 | ||||||||
| Physical Design | 📰 | 🎬 | ||||||||
| D7 | Tools and Infrastructure | 5 | 📚 | 📰 | 🎬 | |||||
| D8 | Make your NPC Support RV32E | 5 | 📚 | 📰 | 🎬 | |||||
| D Stage Tapeout Preparation | ||||||||||
| C Stage | C1 | ELF Files and Linking | 2 | 📚 | 📰 | 🎬 | ||||
| C2 | Devices and I/O | 10 | 📚 | 📰 | 🎬 | |||||
| C3 | Debugging Tips | 2 | 📚 | 📰 | 🎬 | |||||
| C4 | Bus | 10 | 📚 | 📰 | 🎬 | |||||
| C5 | SoC Computer System | 30 | 📚 | 📰Pt.1 📰Pt.2 | 🎬Pt.1 🎬Pt.2 | |||||
| C Stage Tapeout Preparation | ||||||||||
| B Stage | B1 | Exception Handling and Simple Operating Systems | 15 | 📚 | 📰 | 🎬 | ||||
| B2 | Timing Analysis and Optimization | 5 | 📚 | - | - | |||||
| B3 | Performance Optimization and Simple Caching | 20 | 📚 | 📰 | 🎬 | |||||
| B4 | Pipelined Processor | 20 | 📚 | 📰 | 🎬 | |||||
| B Stage Tapeout Preparation | ||||||||||
| A Stage | Multiplier and Divider | 0 | ||||||||
| System call and Application | 0 | |||||||||
| Virtual Memory Management | 0 | |||||||||
| Privilege level and xv6 | 0 | |||||||||
| Boot Linux and Debian | 0 | |||||||||
| Advanced Cache | 0 | |||||||||
| Advanced Branch Prediction | 0 | |||||||||
| A Stage Tapeout Preparation | ||||||||||
| S Stage | To be continued... | 0 | ||||||||
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Other Resources
- The RISC-V Reader: An Open Architecture Atlas By David Patterson and Andrew Wathelet
- Computer Systems: Based on the RISC-V + Linux Platform Edited by Yuan Chunfeng, Yu Zihao, and Chen Lu
- Digital Design and Computer Architecture - Spring 2023, Onur Mutlu@ETH Zurich
- Questioning template
Record of events
- 2025/07/21 - “One Student One Chip” 2025 Summer Workshop
- 2024/07/14 - “One Student One Chip” 2024 Summer Workshop
- 2023/08/25 - Open Source Chip Technology Ecology Forum (formerly "One Student One Chip" Technology Forum)
- 2023/07/02 - 6th "One Student One Chip" Kick-Off Meeting
- 2022/11/20 - Chip Open Source and Agile Design from a Software Engineering Perspective(Yungang Bao)
- 2022/08/28 - The First "One Student One Chip" Technical Forum and the Fifth Launching Meeting
- 2022/03/12 - Hardware-software collaboration capabilities in chip design(Yue Jin, Bohan Hu, Zeyu Gao)