E1 Hardware Description Language

You have already learned the basics of digital circuits and designed simple processors in Logisim. But you have probably also come to realize that Logisim is not suitable for designing more complex circuits. In fact, modern processors are designed using hardware description languages (HDLs). Next, you will learn how to design digital circuits using HDLs.

Although Logisim is not suitable for designing complex circuits, the experience gained from using Logisim should have helped you develop ‘a hardware mindset’: digital circuit design involves only two things, ‘instantiation’ and ‘wiring’. When you use HDL to design digital circuits in the future, you should connect HDL code with your Logisim experience in your mind: You are simply using a different method to design circuits, but fundamentally, you are still doing 'instantiation' and 'wiring'." Therefore, you should be able to visualise the logical structure of the circuit based on the code you write. If you cannot visualize it, you are likely to end up with a circuit that performs poorly, with low frequency, large area, or high power consumption, or even one that does not work as intended.

Additional Recommended Learning Resources for Digital Circuits

• Digital Design and Computer Architecture: If you need to learn some theoretical knowledge of digital circuits during your studies, you can refer to chapters 1 to 5 in this book.
• Introductory Verilog Video
• Verilog Syntax Overview
• Advanced Digital System Design Techniques and Case Studies in Verilog
• USTC Verilog OJ Platform(registration and login required)

Learn Verilog Language through Online Websites

We recommend the Verilog online learning website HDLBits, which provides a wealth of exercises and uses online simulation to determine whether your code is correct.

If you are confident in your Verilog skills, try completing the following exercises:

• Sequential Logic
• Finite State Machines
  • Lemmings 1
  • Lemmings 2
  • Lemmings 3
  • Lemmings 4
  • PS/2 packet parser
  • PS/2 packet parser and datapath
  • Serial receiver
  • Serial receiver and datapath
  • Serial receiver with parity checking

If you find the above exercises very difficult, we recommend that you start with the basic exercises. Specifically, you need to complete the exercises corresponding to the following chapters:

• Getting Started - recommended to complete, to familiarize yourself with the exercise workflow
• Verilog Language - recommended for those not yet familiar with Verilog
• Combinational Logic
  • Basic Gates
    • More logic gates
    • Truth tables
    • Simple circuit A
    • Simple circuit B
    • Thermostat
    • 3-bit population count
    • Even longer vectors
  • Multiplexers
    • 2-to-1 multiplexer
    • 9-to-1 multiplexer
    • 256-to-1 4-bits multiplexer
  • Arithmetic Circuits
    • Signed addition overflow
    • 100-bits binary adder
• Sequential Logic
  • Latches and Flip-Flops
    • D flip-flip
    • DFF with reset value
    • DFF with asynchronous reset
    • DFF with byte enable
    • Mux and DFF
    • Create circuit from truth table
    • Detect an edge
    • Detect both edges
    • Edge capture register
    • Dual-edge triggered flip-flop
  • Counters
    • Decade counter again
    • Slow decade counter
    • Counter 1000
    • 12-hour clock
  • Shift Registers
    • Left/right rotator
    • Left/right arithmetic shift by 1 or 8
    • 5-bits LFSR
    • Shift register
    • 3-input LUT
  • More Circuits - complete all
  • Finite State Machines - complete all

The Relationship between Verilog and Circuit Diagrams

Try to generate the Verilog code corresponding to the circuit in Logisim, then read the code to understand how the Verilog code maps to the corresponding Logisim circuit.

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