module light(
  input clk,
  input rst,
  output reg [15:0] led
);
  reg [31:0] count;
  always @(posedge clk) begin
    if (rst) begin led <= 1; count <= 0; end
    else begin
      if (count == 0) led <= {led[14:0], led[15]};
      count <= (count >= 5000000 ? 32'b0 : count + 1);
    end
  end
endmodule

#define _CONCAT(x, y) x ## y
#define CONCAT(x, y)  _CONCAT(x, y)

#define DEF_WIRE(name, w) uint64_t name : w
#define DEF_REG(name, w)  uint64_t name : w; \
                          uint64_t CONCAT(name, _next) : w; \
                          uint64_t CONCAT(name, _update) : 1

typedef struct {
  DEF_WIRE(clk, 1);
  DEF_WIRE(rst, 1);
  DEF_REG (led, 16);
  DEF_REG (count, 32);
} Circuit;

Circuit circuit;

#define EVAL(c, name, val) do { \
                             c->CONCAT(name, _next) = (val); \
                             c->CONCAT(name, _update) = 1; \
                           } while (0)
#define UPDATE(c, name)    do { \
                             if (c->CONCAT(name, _update)) { \
                               c->name = c->CONCAT(name, _next); \
                             } \
                           } while (0)
static void cycle(Circuit *c) {
  c->led_update = 0;
  c->count_update = 0;
  if (c->rst) {
    EVAL(c, led, 1);
    EVAL(c, count, 0);
  } else {
    if (c->count == 0) {
      EVAL(c, led, (BITS(c->led, 14, 0) << 1) | BITS(c->led, 15, 15));
    }
    EVAL(c, count, c->count >= 5000000 ? 0 : c->count + 1);
  }
  UPDATE(c, led);
  UPDATE(c, count);
}

static void reset(Circuit *c) {
  c->rst = 1;
  cycle(c);
  c->rst = 0;
}

int main() {
  reset(&circuit);
  while (1) {
    cycle(&circuit);
  }
  return 0;
}

#include <stdio.h>
#include <stdint.h>

#define _CONCAT(x, y) x ## y
#define CONCAT(x, y)  _CONCAT(x, y)
#define BITMASK(bits) ((1ull << (bits)) - 1)
// similar to x[hi:lo] in verilog
#define BITS(x, hi, lo) (((x) >> (lo)) & BITMASK((hi) - (lo) + 1))
#define DEF_WIRE(name, w) uint64_t name : w
#define DEF_REG(name, w)  uint64_t name : w; \
                          uint64_t CONCAT(name, _next) : w; \
                          uint64_t CONCAT(name, _update) : 1
#define EVAL(c, name, val) do { \
                             c->CONCAT(name, _next) = (val); \
                             c->CONCAT(name, _update) = 1; \
                           } while (0)
#define UPDATE(c, name)    do { \
                             if (c->CONCAT(name, _update)) { \
                               c->name = c->CONCAT(name, _next); \
                             } \
                           } while (0)

typedef struct {
  DEF_WIRE(clk, 1);
  DEF_WIRE(rst, 1);
  DEF_REG (led, 16);
  DEF_REG (count, 32);
} Circuit;
static Circuit circuit;

static void cycle(Circuit *c) {
  c->led_update = 0;
  c->count_update = 0;
  if (c->rst) {
    EVAL(c, led, 1);
    EVAL(c, count, 0);
  } else {
    if (c->count == 0) {
      EVAL(c, led, (BITS(c->led, 14, 0) << 1) | BITS(c->led, 15, 15));
    }
    EVAL(c, count, c->count >= 5000000 ? 0 : c->count + 1);
  }
  UPDATE(c, led);
  UPDATE(c, count);
}

static void reset(Circuit *c) {
  c->rst = 1;
  cycle(c);
  c->rst = 0;
}

static void display(Circuit *c) {
  static uint16_t last_led = 0;
  if (last_led != c->led) { // only update display when c->led changes
    for (int i = 0; i < 16; i ++) {
      putchar(BITS(c->led, i, i) ? 'o' : '.');
    }
    putchar('\r');
    fflush(stdout);
    last_led = c->led;
  }
}

int main() {
  reset(&circuit);
  while (1) {
    cycle(&circuit);
    display(&circuit);
  }
  return 0;
}

verilator --cc --exe main.cpp light.v  # 通过Verilator将RTL代码编译成仿真程序的C++源文件
make -C obj_dir -f Vlight.mk           # 将C++编译成可执行的仿真程序
./obj_dir/Vlight                       # 启动仿真程序

// obj_dir/Vlight___024root.h
    VL_IN8(clk,0,0);
    VL_IN8(rst,0,0);
    VL_OUT16(led,15,0);
    IData/*31:0*/ light__DOT__count;
    // ...

// obj_dir/Vlight___024root__DepSet_hbb020019__0.cpp
    if (vlSelf->rst) {
        __Vdly__led = 1U;
        __Vdly__light__DOT__count = 0U;
    } else {
        if ((0U == vlSelf->light__DOT__count)) {
            __Vdly__led = ((0xfffeU & ((IData)(vlSelf->led)
                                       << 1U)) | (1U
                                                  & ((IData)(vlSelf->led)
                                                     >> 0xfU)));
        }
        __Vdly__light__DOT__count = ((0x4c4b40U <= vlSelf->light__DOT__count)
                                      ? 0U : ((IData)(1U)
                                              + vlSelf->light__DOT__count));
    }

Intruduction

It was designed ... for a variety of design tools, including verification
simulation, timing analysis, test analysis, and synthesis.

The Verilog HDL is defined in terms of a discrete event execution model. The discrete
event simulation is described in more detail in this subclause to provide a context
to describe the meaning and valid interpretation of Verilog HDL constructs. These
resulting definitions provide the standard Verilog reference model for simulation,
which all compliant simulators shall implement. However, there is a great deal of
choice in the definitions that follow, and differences in some details of execution
are to be expected between different simulators. In addition, Verilog HDL simulators
are free to use different algorithms from those described in this clause, provided
the user-visible effect is consistent with the reference model.

A design consists of connected threads of execution or processes. Processes are
objects that can be evaluated, that may have state, and that can respond to changes
on their inputs to produce outputs. Processes include primitives, modules, initial
and always procedural blocks, continuous assignments, asynchronous tasks, and
procedural assignment statements.

Processes are sensitive to update events. When an update event is executed, all the
processes that are sensitive to that event are evaluated in an arbitrary order. The
evaluation of a process is also an event, known as an evaluation event.

Events can occur at different times. In order to keep track of the events and to
make sure they are processed in the correct order, the events are kept on an event
queue, ordered by simulation time. Putting an event on the queue is called
scheduling an event.

while (there are events) {  // 不断重复如下操作
  if (no active events) {   // R1为空时
    if (there are inactive events) {  // 如果R2不为空
      activate all inactive events;   // 则将R2中的所有事件转移到R1
    } else if (there are nonblocking assign update events) { // 否则, 如果R3不为空
      activate all nonblocking assign update events;  // 则将R3中的所有事件转移到R1
    } else if (there are monitor events) {  // 否则, 如果R4不为空
      activate all monitor events;          // 则将R4中的所有事件转移到R1
    } else {                                  // 否则
      advance T to the next event time;       // 将仿真时刻前进一个单位
      activate all inactive events for time T;// 将R5中当前仿真时刻的事件按类型转移到R1或R3
    }
  }
  E = any active event;  // 从R1中取出一个事件
  if (E is an update event) {    // 如果是更新事件
    update the modified object;  // 更新相应的对象
    // 将对该事件敏感的过程的求值作为求值事件添加到事件队列中
    add evaluation events for sensitive processes to event queue;
  } else {                                 // 如果是求值事件
    evaluate the process;                  // 对过程进行求值
    add update events to the event queue;  // 将赋值行为作为更新事件添加到事件队列中
  }
}

always @(posedge clk) begin
  if (rst) begin led <= 1; count <= 0; end
  else begin
    if (count == 0) led <= {led[14:0], led[15]};
    count <= (count >= 5000000 ? 0 : count + 1);
  end
end

static void cycle(Circuit *c) {
  c->led_update = 0; c->count_update = 0;
  if (c->rst) { EVAL(c, led, 1); EVAL(c, count, 0); }
  else {
    if (c->count == 0) { EVAL(c, led, (BITS(c->led,14,0)<<1) | BITS(c->led,15,15)); }
    EVAL(c, count, c->count >= 5000000 ? 0 : c->count + 1);
  }
  UPDATE(c, led); UPDATE(c, count);
}

always @(posedge clk or negedge rstn) begin
  if (!rstn) a = 1'b0;
  else a = b; // (1)
end

always @(posedge clk or negedge rstn) begin
  if (!rstn) b = 1'b1;
  else b = a; // (2)
end

always @(posedge clk or negedge rstn) begin
  if (!rstn) a = 1'b0;
  else a = 1;
end

always @(posedge clk) begin
  $display("a = %d", a);
end

module top(output [15:0] y);
  initial begin y = 1234; end
  initial begin $display("y = %d", y); end
endmodule

module top(output [15:0] y);
  initial begin $display("y = %d", y); end
  initial begin y = 1234; end
endmodule

#include <stdio.h>
#include "Vtop.h"
int main() {
  static Vtop *top = new Vtop;
  while (1) { top->eval(); }
  return 0;
}

verilator --cc --exe main.cpp top.v
make -C obj_dir -f Vtop.mk
./obj_dir/Vtop